3069RF-ZTAT Datasheet, PDF (442/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is
H'FFFA5 and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address
H'FFFA5 and bits 7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always
read 1.
Address H'FFFA5
Bit
7
6
5
4
3
NDR7 NDR6 NDR5 NDR4
—
Initial value
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
—
Next data 7 to 4
These bits store the next output
data for TPC output group 1
2
1
0
—
—
—
1
1
1
—
—
—
Reserved bits
Address H'FFFA7
Bit
7
6
5
4
3
2
1
0
—
—
—
—
NDR3 NDR2 NDR1 NDR0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
—
R/W R/W
R/W R/W
Reserved bits
Next data 3 to 0
These bits store the next output
data for TPC output group 0
Rev. 5.0, 09/04, page 420 of 978