3069RF-ZTAT Datasheet, PDF (24/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Table 1.1 Features
Feature
CPU
Memory
Interrupt
controller
Bus controller
Description
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers, eight 16-bit registers, or eight 32-bit
registers)
High-speed operation
• Maximum clock rate: 25 MHz
• Add/subtract: 80 ns
• Multiply/divide: 560 ns
16-Mbyte address space
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
• Bit manipulation instructions with register-indirect specification of bit
positions
H8/3069R
• ROM: 512 kbytes
• RAM: 16 kbytes
• Seven external interrupt pins: NMI, IRQ0 to IRQ5
• 36 internal interrupts
• Three selectable interrupt priority levels
• Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Chip select output available for areas 0 to 7
• 8-bit access or 16-bit access selectable for each area
• Two-state or three-state access selectable for each area
• Selection of two wait modes
• Number of program wait states selectable for each area
• Direct connection of burst ROM
• Direct connection of up to 8-Mbyte DRAM (or DRAM interface can be used
as interval timer)
• Bus arbitration function
Rev. 5.0, 09/04, page 2 of 978