3069RF-ZTAT Datasheet, PDF (84/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS₀ to CS₇, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as
outputs or fixed high, or placed in the high-impedance state in software standby mode.
Bit 1
SSOE
0
1
Description
In software standby mode, the address bus and bus control signals are all high-
impedance
(Initial value)
In software standby mode, the address bus retains its output state and bus control
signals are fixed high
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
3.4 Operating Mode Descriptions
3.4.1 Mode 1
Ports 1, 2, and 5 function as address pins A₁₉ to A₀, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. If at least
one area is designated for 16-bit access in ABWCR, the bus mode switches to 16 bits.
3.4.2 Mode 2
Ports 1, 2, and 5 function as address pins A₁₉ to A₀, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all
areas are designated for 8-bit access in ABWCR, the bus mode switches to 8 bits.
3.4.3 Mode 3
Ports 1, 2, 5, and part of port A function as address pins A₂₃ to A₀, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. If at least one area is designated for 16-bit access in ABWCR, the bus mode switches to
16 bits. A₂₃ to A₂₁ are valid when 0 is written in bits 7 to 5 of the bus release control register
(BRCR). (In this mode A₂₀ is always used for address output.)
Rev. 5.0, 09/04, page 62 of 978