3069RF-ZTAT Datasheet, PDF (462/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the WDT.
Overflow
Interrupt signal
Interrupt
(interval timer) ^control
TCNT
TCSR
RSTCSR
Reset
(internal)
Reset control
Clock
Clock
selector
[Legend]
TCNT: Timer counter
TCSR: Timer control/status register
RSTCSR: Reset control/status register
Figure 12.1 WDT Block Diagram
Read/
write
control
Internal
data bus
Internal clock sources
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
12.1.3 Register Configuration
Table 12.1 summarizes the WDT registers.
Table 12.1 WDT Registers
Address*¹
Write*² Read Name
Abbreviation
H'FFF8C H'FFF8C Timer control/status register
TCSR
H'FFF8D Timer counter
TCNT
H'FFF8E H'FFF8F Reset control/status register
RSTCSR
Notes: 1. Lower 20 bits of the address in advanced mode.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7, to clear the flag.
R/W Initial Value
R/(W)*³ H'18
R/W H'00
R/(W)*³ H'3F
Rev. 5.0, 09/04, page 440 of 978