3069RF-ZTAT Datasheet, PDF (149/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

6.2.7 DRAM Control Register A (DRCRA)
Bit
7
6
5
4
DRAS2 DRAS1 DRAS0 —
Initial value
0
0
0
1
Read/Write R/W
R/W
R/W
—
3
BE
0
R/W
2
RDM
0
R/W
1
0
SRFMD RFSHE
0
R/W
0
R/W
DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface
function, and the access mode, and enables or disables self-refreshing and refresh pin output.
DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 5—DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5 are
to function as DRAM interface areas (DRAM space) in expanded mode, and at the same time
select the RAS output pin corresponding to each DRAM space.
Description
Bit 7 Bit 6 Bit 5
DRAS2 DRAS1 DRAS0 Area 5
Area 4
Area 3
Area 2
0
0
0
Normal
Normal
Normal
Normal
1
Note:
1
Normal
Normal
Normal
DRAM space
(CS₂)
1
0
Normal
Normal
DRAM space DRAM space
(CS )
3
(CS )
2
1
Normal
Normal
DRAM space DRAM space
(CS₂)*
(CS₂)*
0
0
Normal
DRAM space DRAM space DRAM space
(CS₄)
(CS₃)
(CS₂)
1
DRAM space DRAM space DRAM space DRAM space
(CS )
5
(CS )
4
(CS )
3
(CS )
2
1
0
DRAM space DRAM space DRAM space DRAM space
(CS₄)*
(CS₄)*
(CS₂)*
(CS₂)*
1
DRAM space DRAM space DRAM space DRAM space
(CS₂)*
(CS₂)*
(CS₂)*
(CS₂)*
* A single CSn pin serves as a common RAS output pin for a number of areas. Unused
CSn pins can be used as input/output ports.
When any of bits DRAS2 to DRAS0 is set to 1 in expanded mode, it is not possible to write to
DRCRB, RTMCSR, RTCNT, or RTCOR. However, 0 can be written to the CMF flag in
RTMCSR to clear the flag.
Rev. 5.0, 09/04, page 127 of 978