3069RF-ZTAT Datasheet, PDF (328/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Pin
Pin Functions and Selection Method
PB /TP /
3
11
TMIO /
3
DREQ /CS
1
4
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR3, bits
CCLR1 and CCLR0 in 8TCR3, bit CS4E in CSCR, bit NDER11 in NDERB, and bit PB DDR select the pin
3
function as follows.
DRAM interface
settings
(1) in table below
(2) in table
below
OIS3/2 and OS1/0
All 0
Not all 0
—
CS4E
PB DDR
3
NDER11
0
1
—
—
0
1
1
—
—
—
—
0
1
—
—
—
Pin function
PB
3
input
PB
3
output
TP
11
output
CS
4
output
TMIO output
3
CS
4
output*³
TMIO
3
input*¹
DREQ input*2
1
Notes: 1. TMIO input when CCLR1 = CCLR0 = 1.
3
2. When an external request is specified as a DMAC activation source, DREQ input regardless of
1
bits OIS3 and OIS2, OS1 and OS0, CCLR1 and CCLR0, CS4E, NDER11, and PB DDR.
3
3. CS is output as RAS .
4
4
DRAM interface
(1)
settings
(2)
(1)
DRAS2
0
1
DRAS1
0
1
0
1
DRAS0
0
1
0
1
0
1
0
1
PB /TP /
2
10
TMO /CS
2
5
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and OS1/0 in 8TCSR2, bit
CS5E in CSCR, bit NDER10 in NDERB, and bit PB DDR select the pin function as follows.
2
DRAM interface
settings
(1) in table below
(2) in table
below
OIS3/2 and OS1/0
All 0
Not all 0
—
CS5E
0
1
—
—
PB DDR
2
NDER10
0
1
1
—
—
—
—
0
1
—
—
—
Pin function
PB
2
input
PB
2
output
TP
10
output
CS
5
output
TMIO output
2
CS
5
output*
Note:
*
CS
5
is
output
as
RAS .
5
DRAM interface
(1)
settings
(2)
(1)
DRAS2
0
1
DRAS1
0
1
0
1
DRAS0
0
1
0
1
0
1
0
1
Rev. 5.0, 09/04, page 306 of 978