3069RF-ZTAT Datasheet, PDF (170/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

16-Bit, Three-State-Access Areas
Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In
these areas, the upper data bus (D₁₅ to D₈) is used in accesses to even addresses and the lower data
bus (D₇ to D₀) in accesses to odd addresses. Wait states can be inserted.
φ
Address bus
CSn
AS
RD
Read access ^D15 ^{to D}8
D7 to D0
HWR
Write access
LWR
D15 to D8
D7 to D0
Bus cycle
T1
T2
T3
Even external address in area n
Valid
Invalid
High
Valid
Undetermined data
Note: n = 7 to 0
Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
(Byte Access to Even Address)
Rev. 5.0, 09/04, page 148 of 978