3069RF-ZTAT Datasheet, PDF (641/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

For the settable range of the FPEFEQ parameter, see section 21.4.1, Clock Timing.
When the frequency is set out of this range, an error is returned to the FPFR parameter
of the initialization program and initialization is not performed. For details on the
frequency setting, see the description in 18.4.3(2) (a) Flash programming/erasing
frequency parameter (FPEFEQ: general register ER0 of CPU).
• The start address in the user branch destination is set to the FUBRA parameter (general
register: ER1).
Not available in the H8/3069R, 0 must be set to FUBRA.
When the user branch is executed, the branch destination is executed in a user MAT
other than the one that is to be programmed. The area of the on-chip program that is
downloaded cannot be set.
The program processing must be returned from the user branch processing by the RTS
instruction.
See the description in 18.4.3 (2) (b) Flash user branch address setting parameter
(FUBRA: general register ER1 of CPU).
(g) Initialization
When a programming program is downloaded, the initialization program is also downloaded
to the on-chip RAM. There is an entry point of the initialization program in the area from
(download start address set by FTDAR) + 32 bytes. The subroutine is called and initialization
is executed by using the following steps.
MOV.L #DLTOP+32,ER2
; Set entry address to ER2
JSR
@ER2
; Call initialization routine
NOP
• The general registers other than R0L are saved in the initialization program.
• R0L is a return value of the FPFR parameter.
• Since the stack area is used in the initialization program, a stack area of a maximum
128 bytes must be saved in RAM.
• Interrupts can be accepted during the execution of the initialization program. The
program storage area and stack area in the on-chip RAM and register values must not
be destroyed.
(h) The return value in the initialization program, FPFR (general register R0L) is judged.
(i) All interrupts and the use of a bus master other than the CPU are prohibited.
The specified voltage is applied for the specified time when programming or erasing. If
interrupts occur or the bus mastership is moved to other than the CPU during this time, more
than the specified voltage will be applied and flash memory may be damaged. Therefore,
interrupts and movement of bus mastership to DMAC or BREQ and DRAM refresh other than
the CPU are prohibited.
Rev. 5.0, 09/04, page 619 of 978