3069RF-ZTAT Datasheet, PDF (218/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

7.1.2 Block Diagram
Figure 7.1 shows a DMAC block diagram.
Internal address bus
Internal
interrupts
IMIA0
IMIA1
IMIA2
ADI
TXI0
RXI0
DREQ₀
DREQ₁
TEND₀
TEND₁
Interrupt
signals
DEND0A
DEND0B
DEND1A
DEND1B
Control logic
DTCR0A
DTCR0B
DTCR1A
DTCR1B
Data buffer
Channel
0
Channel
0A
Channel
0B
Channel
1
Channel
1A
Channel
1B
Address buffer
Arithmetic-logic unit
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
Internal data bus
[Legend]
DTCR: Data transfer control register
MAR: Memory address register
IOAR: I/O address register
ETCR: Execute transfer count register
Figure 7.1 Block Diagram of DMAC
Rev. 5.0, 09/04, page 196 of 978