3069RF-ZTAT Datasheet, PDF (315/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

standby mode it retains its previous setting. Therefore, if a transition is made to software standby
mode while port A is functioning as an input/output port and a PADDR bit is set to 1, the
corresponding pin maintains its output state.
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output
data for port A. When port A functions as an output port, the value of this register is output. When
a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read.
Bit
Initial value
Read/Write
7
PA ₇
0
R/W
6
PA ₆
0
R/W
5
PA ₅
0
R/W
4
PA ₄
0
R/W
3
PA ₃
0
R/W
2
PA ₂
0
R/W
1
PA ₁
0
R/W
Port A data 7 to 0
These bits store data for port A pins
0
PA ₀
0
R/W
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Table 8.19 Port A Pin Functions (Modes 1, 2, 7)
Pin
PA7/TP7/
TIOCB
2
Pin Functions and Selection Method
Bit PWM2 in TMDR, bits IOB2 to IOB0 in TIOR2, bit NDER7 in NDERA, and bit PA7DDR select the pin function
as follows.
16-bit timer channel 2
settings
(1) in table below
(2) in table below
PA DDR
7
NDER7
—
0
1
1
—
—
0
1
Pin function
TIOCB output
2
Note:
*
TIOCB input when IOB2 = 1 and PWM2 = 0.
2
16-bit timer channel 2
settings
(2)
(1)
PA input PA output TP output
7
7
7
TIOCB
2
input*
(2)
IOB2
0
1
IOB1
0
0
1
—
IOB0
0
1
—
—
Rev. 5.0, 09/04, page 293 of 978