3069RF-ZTAT Datasheet, PDF (184/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only
UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0,
PB5 can be used as an input/output port.
Note that RAS down mode cannot be used when a device other than DRAM is connected to
external space and HWR and LWR are used as write strobes. In this case, also, an idle cycle (Ti)
is always inserted when an external access to other than DRAM space occurs after a DRAM space
access. For details, see section 6.9, Idle Cycle.
Table 6.8 CSEL Settings and UCAS and LCAS Output Pins
CSEL
0
1
UCAS
PB₄
HWR
LCAS
PB₅
LWR
Figure 6.21 shows the control timing.
Tp
Tr
Tc1
Tc2
φ
A23 to A0
Row
Column
CSn (RAS)
Byte control
PB₄(UCAS)
PB₅(LCAS)
RD(WE)
Note: n = 2 to 5
Figure 6.21 Control Timing (Upper-Byte Write Access When CSEL = 0)
Rev. 5.0, 09/04, page 162 of 978