3069RF-ZTAT Datasheet, PDF (105/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level masking by the I and UI bits in the CPU condition code register (CCR)
• Seven external interrupt pins
NMI has the highest priority and is always accepted*; either the rising or falling edge can be
selected. For each of IRQ₀ to IRQ₅, sensing of the falling edge or level sensing can be selected
independently.
Note: * NMI input is sometimes disabled when flash memory is being programmed or erased. For
details see section 18.4.5 Flash Vector Address Control Register (FVACR).
Rev. 5.0, 09/04, page 83 of 978