3069RF-ZTAT Datasheet, PDF (987/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

P6₇/φ
Access to external
memory
T1
T2
T3
RES
Internal reset
signal
A₂₃ to A₀
High impedance
AS, RD
(read)
HWR, LWR
(write)
D₁₅ to D₀
(write)
I/O port,
CS₇ to CS₁
High impedance
High impedance
Figure D.3 Reset during Memory Access (Mode 5)
Mode 7: Figure D.4 is a timing diagram for the case in which RES goes low during an operation
in mode 7. As soon as RES goes low, all ports and clock pin P6₇/φ are initialized to the input state.
P6₇/φ
4-5
Internal reset
signal
I/O port
High impedance
High impedance
Figure D.4 Reset during Operation (Mode 7)
Rev. 5.0, 09/04, page 965 of 978