3069RF-ZTAT Datasheet, PDF (272/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

When 16-bit timer interrupt activates the DMAC, make sure the next interrupt does not occur
before the DMA transfer ends. If one 16-bit timer interrupt activates two or more channels, make
sure the next interrupt does not occur before the DMA transfers end on all the activated channels.
If the next interrupt occurs before a transfer ends, the channel or channels for which that interrupt
was selected may fail to accept further activation requests.
7.6.6 NMI Interrupts and Block Transfer Mode
If an NMI interrupt occurs in block transfer mode, the DMAC operates as follows.
• When the NMI interrupt occurs, the DMAC finishes transferring the current byte or word, then
clears the DTME bit to 0 and halts. The halt may occur in the middle of a block.
It is possible to find whether a transfer was halted in the middle of a block by checking the
block size counter. If the block size counter does not have its initial value, the transfer was
halted in the middle of a block.
• If the transfer is halted in the middle of a block, the activating interrupt flag is cleared to 0.
The activation request is not held pending.
• While the DTE bit is set to 1 and the DTME bit is cleared to 0, the DMAC is halted and does
not accept activating interrupt requests. If an activating interrupt occurs in this state, the
DMAC does not operate and does not hold the transfer request pending internally. Neither is a
CPU interrupt requested.
For this reason, before setting the DTME bit to 1, first clear the enable bit of the activating
interrupt to 0. Then, after setting the DTME bit to 1, set the interrupt enable bit to 1 again. See
section 7.6.5, Note on Activating DMAC by Internal Interrupts.
• When the DTME bit is set to 1, the DMAC waits for the next transfer request. If it was halted
in the middle of a block transfer, the rest of the block is transferred when the next transfer
request occurs. Otherwise, the next block is transferred when the next transfer request occurs.
7.6.7 Memory and I/O Address Register Values
Table 7.14 indicates the address ranges that can be specified in the memory and I/O address
registers (MAR and IOAR).
Rev. 5.0, 09/04, page 250 of 978