3069RF-ZTAT Datasheet, PDF(259/1003 Page) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

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3069RF-ZTAT Datasheet, PDF (259/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

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Figure 7.15 shows an auto-requested burst-mode transfer. This example shows a transfer of three

words from a 16-bit two-state access area to another 16-bit two-state access area.

CPU cycle

DMAC cycle

CPU cycle

T1 T2 Td T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 T1 T2

Ï

Address

bus

RD

Source Destination

address address

HWR,

LWR

Figure 7.15 Burst DMA Bus Timing

When the DMAC is activated from a DREQ pin there is a minimum interval of four states from

when the transfer is requested until the DMAC starts operating. The DREQ pin is not sampled

during the time between the transfer request and the start of the transfer. In short address mode

and normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the

pin is next sampled at the end of one block transfer.

Rev. 5.0, 09/04, page 237 of 978

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