3069RF-ZTAT Datasheet, PDF (629/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Bit 3—RAM Select (RAMS): Sets whether the user MAT is emulated or not. When RAMS = 1,
all blocks of the user MAT are in the programming/erasing protection state.
Bit 3
RAMS
0
1
Description
Emulation is not selected
Programming/erasing protection of all user-MAT blocks is invalid
Emulation is selected
Programming/erasing protection of all user-MAT blocks is valid
(Initial value)
Bits 2 to 0—User MAT Area Select: These bits are used with bit 3 and select the user-MAT area
to be overlapped with the on-chip RAM (see table 18.7).
Table 18.7 Division of User MAT Area
RAM Area
H'FFE000 to H'FFEFFF
H'000000 to H'000FFF
H'001000 to H'001FFF
H'002000 to H'002FFF
H'003000 to H'003FFF
H'004000 to H'004FFF
H'005000 to H'005FFF
H'006000 to H'006FFF
H'007000 to H'007FFF
Note: * Don't care.
Block Name
RAM area (4 kbytes)
EB0 (4kbytes)
EB1 (4kbytes)
EB2 (4kbytes)
EB3 (4kbytes)
EB4 (4kbytes)
EB5 (4kbytes)
EB6 (4kbytes)
EB7 (4kbytes)
RAMS
0
1
1
1
1
1
1
1
1
RAM2
*
0
0
0
0
1
1
1
1
RAM1
*
0
0
1
1
0
0
1
1
RAM0
*
0
1
0
1
0
1
0
1
18.4.5 Flash Vector Address Control Register (FVACR)
FVACR modifies the space which reads the vector table data of the NMI interrupts. Normally the
vector table data is read from the address spaces from H'00001C to H'00004F. However, the
vector table can be read from the internal I/O register (FVADRR to FVADRL) by the FVACR
setting. FVACR is initialized to H'00 at a power-on reset or in hardware standby mode.
All interrupts including NMI must be prohibited in the programming/erasing processing or during
downloading on-chip program. When if it is not possible to avoid using the NMI interrupt due to
system requirements, such as during system error processing, FVACR and FVADRR to FVADRL
must be set and the interrupt exception processing routine must be set in the on-chip RAM.
Rev. 5.0, 09/04, page 607 of 978