3069RF-ZTAT Datasheet, PDF (898/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

TISRB—Timer Interrupt Status Register B
H'FFF65
16-bit timer (all channels)
Bit:
Initial value:
Read/Write:
7
6
5
4
3
2
1
0
— IMIEB2 IMIEB1 IMIEB0 — IMFB2 IMFB1 IMFB0
1
0
0
0
1
0
0
0
— R/W R/W R/W — R/(W)* R/(W)* R/(W)*
Input capture/compare match flag B0
[Clearing condition]
0
Read IMFB0 when IMFB0=1, then write 0 in IMFB0.
(Initial value)
[Setting conditions]
TCNT0=GRB0 when GRB0 functions as an output compare register.
1 _{TCNT0 value is transferred to GRB0 by an input capture signal when GRB0}
functions as an input capture register.
Input capture/compare match flag B1
0 ^{[Clearing condition]}
Read IMFB1 when IMFB1=1, then write 0 in IMFB1.
(Initial value)
[Setting conditions]
TCNT1=GRB1 when GRB1 functions as an output compare register.
1 _{TCNT1 value is transferred to GRB1 by an input capture signal when GRB1}
functions as an input capture register.
Input capture/compare match flag B2
0 ^{[Clearing condition]}
Read IMFB2 when IMFB2=1, then write 0 in IMFB2.
(Initial value)
[Setting conditions]
TCNT2=GRB2 when GRB2 functions as an output compare register.
1 _{TCNT2 value is transferred to GRB2 by an input capture signal when GRB2}
functions as an input capture register.
Input capture/compare match interrupt enable B0
0 IMIB0 interrupt requested by IMFB0 flag is disabled
1 IMIB0 interrupt requested by IMFB0 flag is enabled
(Initial value)
Input capture/compare match interrupt enable B1
0 IMIB1 interrupt requested by IMFB1 flag is disabled
1 IMIB1 interrupt requested by IMFB1 flag is enabled
(Initial value)
Input capture/compare match interrupt enable B2
0 IMIB2 interrupt requested by IMFB2 flag is disabled
1 IMIB2 interrupt requested by IMFB2 flag is enabled
(Initial value)
Note : * Only 0 can be written, to clear the flag.
Rev. 5.0, 09/04, page 876 of 978