3069RF-ZTAT Datasheet, PDF (466/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock
sources, obtained by prescaling the system clock (φ), for input to TCNT.
Bit 2
CKS2
0
1
Bit 1
CKS1
0
1
0
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
Description
φ/2
φ /32
φ /64
φ /128
φ /256
φ /512
φ /2048
φ /4096
(Initial value)
12.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Bit
7
6
5
4
3
2
1
0
WRST
—
—
—
—
—
—
—
Initial value
0
0
1
1
1
1
1
1
Read/Write R/(W)* R/W
—
—
—
—
—
—
Reserved bits
Watchdog timer reset
Indicates that a reset signal has been generated
Notes: RSTCSR is write-protected by a password. For details see section 12.2.4, Notes on
Register Access.
* Only 0 can be written in bit 7, to clear the flag.
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Rev. 5.0, 09/04, page 444 of 978