3069RF-ZTAT Datasheet, PDF(264/1003 Page) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

3069RF-ZTAT Datasheet, PDF (264/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

◁

DMAC cycle

(channel 1)

CPU

cycle

DMAC cycle

(channel 0A)

CPU

cycle

DMAC cycle

(channel 1)

T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 Td T1 T2 T1 T2

Ï

Address

bus

RD

HWR ,

LWR

Figure 7.19 Timing of Multiple-Channel Operations

7.4.10 External Bus Requests, DRAM Interface, and DMAC

During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or

by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer

of the current byte or word. If there is a transfer request at this point, the DMAC requests the bus

right again. Figure 7.20 shows an example of the timing of insertion of a refresh cycle during a

burst transfer on channel 0.

DMAC cycle (channel 0)

Refresh

cycle

DMAC cycle (channel 0)

T1 T2 T1 T2 T1 T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2

Ï

Address

bus

RD

HWR , LWR

Figure 7.20 Bus Timing of DRAM Interface, and DMAC

Rev. 5.0, 09/04, page 242 of 978

▷