3069RF-ZTAT Datasheet, PDF (473/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

12.4 Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
12.5 Usage Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated
during the T₃ state of a write cycle to TCNT, the write takes priority and the timer count is not
incremented. See figure 12.8.
CPU: TCNT write cycle
T₁
T₂
T₃
φ
TCNT
Internal write
signal
TCNT input
clock
TCNT
N
M
Counter write data
Figure 12.8 Contention between TCNT Write and Count up
Changing CKS2 to CKS0 Bit: Halt TCNT by clearing the TME bit to 0 in TCSR before
changing the values of bits CKS2 to CKS0.
Rev. 5.0, 09/04, page 451 of 978