3069RF-ZTAT Datasheet, PDF (314/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

8.11.2 Register Descriptions
Table 8.18 summarizes the registers of port A.
Table 8.18 Port A Registers
Initial Value
Address* Name
Abbreviati R/W
on
Modes 1, 2, 5, and 7
Modes 3, 4
H'EE009 Port A data direction PADDR W
register
H'00
H'80
H'FFFD9 Port A data register PADR
R/W H'00
H'00
Note: * Lower 20 bits of the address in advanced mode.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
Bit
7
6
5
4
3
2
1
0
PA₇DDR PA₆DDR PA₅DDR PA₄DDR PA₃DDR PA₂DDR PA₁DDR PA₀DDR
Modes ^{Initial value 1}
0
0
0
0
0
0
0
3, 4 _{Read/Write —}
W
W
W
W
W
W
W
Modes
1, 2, 5,
Initial value
0
0
0
0
0
0
0
0
and 7 ^Read/Write W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
The pin functions that can be selected for pins PA₇ to PA₄ differ between modes 1, 2, and 7, and
modes 3 to 5. For the method of selecting the pin functions, see tables 8.19 and 8.20.
The pin functions that can be selected for pins PA₃ to PA₀ are the same in modes 1 to 5, 7. For the
method of selecting the pin functions, see table 8.21.
When port A functions as an input/output port, a pin in port A becomes an output port if the
corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4,
PA₇DDR is fixed at 1 and PA₇ functions as the A₂₀ address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software
Rev. 5.0, 09/04, page 292 of 978