3069RF-ZTAT Datasheet, PDF (246/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

The transfer count is specified as an 8-bit value in ETCRH and ETCRL. The maximum transfer
count is 255, obtained by setting both ETCRH and ETCRL to H'FF.
Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0,
conversion-end interrupts from the A/D converter, and external request signals.
For the detailed settings see section 7.2.4, Data Transfer Control Registers (DTCR).
Figure 7.7 shows a sample setup procedure for repeat mode.
Repeat mode
Set source and
destination addresses
Set transfer count
Read DTCR
[1] Set the source and destination addresses in MAR
and IOAR. The transfer direction is determined
automatically from the activation source.
[2] Set the transfer count in both ETCRH and ETCRL.
[1] _{[3] Read DTCR while the DTE bit is cleared to 0.}
[4] Set the DTCR bits as follows.
• Select the DMAC activation source with bits
DTS2 to DTS0.
• Clear the DTIE bit to 0 and set the RPE bit to 1
[2]
to select repeat mode.
• Select MAR increment or decrement with the DTID bit.
• Select byte size or word size with the DTSZ bit.
• Set the DTE bit to 1 to enable the transfer.
[3]
Set DTCR
[4]
Repeat mode
Figure 7.7 Repeat Mode Setup Procedure (Example)
Rev. 5.0, 09/04, page 224 of 978