3069RF-ZTAT Datasheet, PDF (119/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

5.3 Interrupt Sources
The interrupt sources include external interrupts (NMI, IRQ₀ to IRQ₅) and 36 internal interrupts.
5.3.1 External Interrupts
There are seven external interrupts: NMI and IRQ₀ to IRQ₅. Of these, NMI, IRQ₀, IRQ₁, and IRQ₂
can be used to exit software standby mode.
NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I
and UI bits in CCR*. The NMIEG bit in SYSCR selects whether an interrupt is requested by the
rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector
number 7.
Note: * NMI input is sometimes disabled when flash memory is being programmed or erased. For
details see section 18.4.5, Flash Vector Address Control Register (FVACR).
IRQ₀ to IRQ₅ Interrupts: These interrupts are requested by input signals at pins IRQ₀ to IRQ₅.
The IRQ₀ to IRQ₅ interrupts have the following features.
• ISCR settings can select whether an interrupt is requested by the low level of the input at pins
IRQ₀ to IRQ₅, or by the falling edge.
• IER settings can enable or disable the IRQ₀ to IRQ₅ interrupts. Interrupt priority levels can be
assigned by four bits in IPRA (IPRA7 to IPRA4).
• The status of IRQ₀ to IRQ₅ interrupt requests is indicated in ISR. The ISR flags can be cleared
to 0 by software.
Figure 5.2 shows a block diagram of interrupts IRQ₀ to IRQ₅.
IRQnSC
IRQnE
IRQn input
Edge/level
sense circuit
IRQnF
S
Q
R
Clear signal
IRQn interrupt
request
Note: n = 5 to 0
Figure 5.2 Block Diagram of Interrupts IRQ₀ to IRQ₅
Rev. 5.0, 09/04, page 97 of 978