3069RF-ZTAT Datasheet, PDF (897/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

TISRA—Timer Interrupt Status Register A
H'FFF64
16-bit timer (all channels)
Bit:
Initial value:
Read/Write:
7
6
5
4
3
2
1
0
— IMIEA2 IMIEA1 IMIEA0 — IMFA2 IMFA1 IMFA0
1
0
0
0
1
0
0
0
— R/W R/W R/W — R/(W)* R/(W)* R/(W)*
Input capture/compare match flag A0
[Clearing conditions]
0 Read IMFA0 when IMFA0=1, then write 0 in IMFA0
DMAC activated by IMIA0 interrupt.
(Initial value)
[Setting conditions]
TCNT0=GRA0 when GRA0 functions as an output compare register.
1 _{TCNT0 value is transferred to GRA0 by an input capture signal when GRA0}
functions as an input capture register.
Input capture/compare match flag A1
[Clearing conditions]
0 Read IMFA1 when IMFA1=1, then write 0 in IMFA1
DMAC activated by IMIA1 interrupt.
(Initial value)
[Setting conditions]
TCNT1=GRA1 when GRA1 functions as an output compare register.
1 _{TCNT1 value is transferred to GRA1 by an input capture signal when GRA1}
functions as an input capture register.
Input capture/compare match flag A2
[Clearing conditions]
0 Read IMFA2 when IMFA2=1, then write 0 in IMFA2
DMAC activated by IMIA2 interrupt.
(Initial value)
[Setting conditions]
TCNT2=GRA2 when GRA2 functions as an output compare register.
1 _{TCNT2 value is transferred to GRA2 by an input capture signal when GRA2}
functions as an input capture register.
Input capture/compare match interrupt enable A0
0 IMIA0 interrupt requested by IMFA0 flag is disabled
1 IMIA0 interrupt requested by IMFA0 flag is enabled
(Initial value)
Input capture/compare match interrupt enable A1
0 IMIA1 interrupt requested by IMFA1 flag is disabled
1 IMIA1 interrupt requested by IMFA1 flag is enabled
(Initial value)
Input capture/compare match interrupt enable A2
0 IMIA2 interrupt requested by IMFA2 flag is disabled
1 IMIA2 interrupt requested by IMFA2 flag is enabled
(Initial value)
Note: * Only 0 can be written, to clear the flag.
Rev. 5.0, 09/04, page 875 of 978