3069RF-ZTAT Datasheet, PDF (179/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Table 6.6 Settings of Bits MXC1 and MXC0 and Address Multiplexing Method
DRCRB
Column
Address
Address Pins
MXC1 MXC0 Bits
Row
0
0
8 bits
address
A₂₃ to A₁₃ A₁₂ A₁₁ A₁₀ A₉ A₈ A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀
A₂₃ to A₁₃ A₂₀* A₁₉ A₁₈ A₁₇ A₁₆ A₁₅ A₁₄ A₁₃ A₁₂ A₁₁ A₁₀ A₉ A₈
1
9 bits
A₂₃ to A₁₃ A₁₂ A₂₀* A₁₉ A₁₈ A₁₇ A₁₆ A₁₅ A₁₄ A₁₃ A₁₂ A₁₁ A₁₀ A₉
1
0
10 bits
A₂₃ to A₁₃ A₁₂ A₁₁ A₂₀* A₁₉ A₁₈ A₁₇ A₁₆ A₁₅ A₁₄ A₁₃ A₁₂ A₁₁ A₁₀
1
Illegal
—
setting
—————————————
Column — — —
address
A₂₃ to A₁₃ A₁₂ A₁₁ A₁₀ A₉ A₈ A₇ A₆ A₅ A₄ A₃ A₂ A₁ A₀
Note:
*
Row address bit A is not multiplexed in 1-Mbyte mode.
20
6.5.4 Data Bus
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, × 16-bit organization DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D₁₅ to D₈, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D₁₅ to D₀, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data
Size and Data Alignment.
6.5.5 Pins Used for DRAM Interface
Table 6.7 shows the pins used for DRAM interfacing and their functions.
Rev. 5.0, 09/04, page 157 of 978