3069RF-ZTAT Datasheet, PDF (867/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

DRCRB—DRAM Control Register B
H'EE027
DRAM interface
Bit
Initial value
Read/Write
7
6
5
4
3
MXC1 MXC0 CSEL RCYCE
0
0
0
0
1
R/W R/W R/W R/W
2
1
0
TPC RCW RLW
0
0
0
R/W R/W R/W
Refresh cycle wait control
0 Wait state (T_RW) insertion is disabled
1 1 wait state (T_RW) is inserted
RAS-CAS wait
0 Wait state (T_rw) insertion is disabled
1 1 wait state (T_rw) is inserted
TP cycle control
0 1-state precharge cycle is inserted
1 2-state precharge cycle is inserted
Refresh cycle enable
0 Refresh cycles are disabled
1 DRAM refresh cycles are enabled
CAS output pin select
0 PB4 and PB5 selected as UCAS and LCAS output pins
1 HWR and LWR selected as UCAS and LCAS output pins
Multiplex control 1 and 0
MXC1 MXC0
Description
0
0 Column address: 8 bits
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4, 5 8-bit access space
16-bit access space
1 ^{Column address: 9 bits}
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4, 5 8-bit access space
16-bit access space
1
0 ^{Column address: 10 bits}
Compared address:
Modes 1, 2
8-bit access space
16-bit access space
Modes 3, 4, 5 8-bit access space
16-bit access space
1 Illegal setting
A₁₉ to A₈
A₁₉ to A₉
A₂₃ to A₈
A₂₃ to A₉
A₁₉ to A₉
A₁₉ to A₁₀
A₂₃ to A₉
A₂₃ to A₁₀
A₁₉ to A₁₀
A₁₉ to A₁₁
A₂₃ to A₁₀
A₂₃ to A₁₁
Rev. 5.0, 09/04, page 845 of 978