3069RF-ZTAT Datasheet, PDF (390/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T₃ state of a general register read cycle, the value before input capture is read.
See figure 9.42.
General register read cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal read signal
Input capture signal
GR
X
M
Internal data bus
X
Figure 9.42 Contention between General Register Read and Input Capture
Rev. 5.0, 09/04, page 368 of 978