3069RF-ZTAT Datasheet, PDF (17/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

11.4.2 Note on Non-Overlapping Output ....................................................................... 437
Section 12 Watchdog Timer ..............................................................................439
12.1 Overview........................................................................................................................... 439
12.1.1 Features................................................................................................................ 439
12.1.2 Block Diagram ..................................................................................................... 440
12.1.3 Register Configuration......................................................................................... 440
12.2 Register Descriptions ........................................................................................................ 441
12.2.1 Timer Counter (TCNT)........................................................................................ 441
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 442
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 444
12.2.4 Notes on Register Access..................................................................................... 445
12.3 Operation .......................................................................................................................... 447
12.3.1 Watchdog Timer Operation ................................................................................. 447
12.3.2 Interval Timer Operation ..................................................................................... 448
12.3.3 Timing of Setting of Overflow Flag (OVF)......................................................... 449
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 450
12.4 Interrupts........................................................................................................................... 451
12.5 Usage Notes ...................................................................................................................... 451
Section 13 Serial Communication Interface ......................................................453
13.1 Overview........................................................................................................................... 453
13.1.1 Features................................................................................................................ 453
13.1.2 Block Diagram ..................................................................................................... 455
13.1.3 Input/Output Pins................................................................................................. 456
13.1.4 Register Configuration......................................................................................... 457
13.2 Register Descriptions ........................................................................................................ 458
13.2.1 Receive Shift Register (RSR)............................................................................... 458
13.2.2 Receive Data Register (RDR) .............................................................................. 458
13.2.3 Transmit Shift Register (TSR) ............................................................................. 459
13.2.4 Transmit Data Register (TDR)............................................................................. 459
13.2.5 Serial Mode Register (SMR)................................................................................ 460
13.2.6 Serial Control Register (SCR).............................................................................. 464
13.2.7 Serial Status Register (SSR)................................................................................. 469
13.2.8 Bit Rate Register (BRR)....................................................................................... 474
13.3 Operation .......................................................................................................................... 481
13.3.1 Overview.............................................................................................................. 481
13.3.2 Operation in Asynchronous Mode ....................................................................... 483
13.3.3 Multiprocessor Communication........................................................................... 493
13.3.4 Synchronous Operation........................................................................................ 499
13.4 SCI Interrupts.................................................................................................................... 508
13.5 Usage Notes ...................................................................................................................... 508
13.5.1 Notes on Use of SCI ............................................................................................ 508
Rev. 5.0, 09/04, page xiii of xviii