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3069RF-ZTAT Datasheet, PDF (787/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
φ
A23 to A0
Tp
tAD
CS5 to CS2
(RAS5 to RAS2)
UCAS, LCAS
(read)
Tr
TC1
tAD
tAD
tAS1
tRP
tRAH
tRAD1
tASD
TC2
tCAS1
tRAD2
tCASD2
tCP
RD (WE)
(read)
D15 to D0
(read)
UCAS, LCAS
(write)
RD (WE)
(write)
D15 to D0
(write)
High
tRAC
tAA
tRDS
tRDH*
tCAC
tCASD1
tASD
tCAS2
tCASD2
tCP
tWCD
tWCS
tWDD tWDS
tWCH
tWDH
RFSH
High
Note: * Specification from the earliest negation timing of RAS and CAS.
Figure 21.19 DRAM Bus Timing (Read/Write)
Rev. 5.0, 09/04, page 765 of 978