3069RF-ZTAT Datasheet, PDF (185/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

6.5.10 Burst Operation
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making a
number of consecutive accesses to the same row address. This mode enables fast (burst) access of
data by simply changing the column address after the row address has been output. Burst access
can be selected by setting the BE bit to 1 in DRCRA.
Burst Access (Fast Page Mode) Operation Timing: Figure 6.22 shows the operation timing for
burst access. When there are consecutive access cycles for DRAM space, the column address and
CAS signal output cycles (two states) continue as long as the row address is the same for
consecutive access cycles. In burst access, too, the bus cycle can be extended by inserting wait
states between T_c1 and T_c2. The wait state insertion method and timing are the same as for full
access: see section 6.5.8, Wait Control, for details.
The row address used for the comparison is determined by the bus width of the relevant area set in
bits MXC1 and MXC0 in DRCRB, and in ABWCR. Table 6.9 shows the compared row addresses
corresponding to the various settings of bits MXC1 and MXC0, and ABWCR.
Tp
Read access
φ
A23 to A0
AS
CSn(RAS)
PB₄/PB₅
(UCAS /LCAS)
RD(WE)
Write access
D15 to D0
PB₄/PB₅
(UCAS/LCAS)
RD(WE)
D15 to D0
Note: n = 2 to 5
Tr
Tc1
Tc2
Tc1
Tc2
Row
Column 1
High level
Column 2
Figure 6.22 Operation Timing in Fast Page Mode
Rev. 5.0, 09/04, page 163 of 978