3069RF-ZTAT Datasheet, PDF (153/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (T_P) is to
be used for DRAM read/write cycles and CAS-before-RAS refresh cycles.
The setting of this bit does not affect the self-refresh function.
Bit 2
TPC
0
1
Description
1-state precharge cycle inserted
2-state precharge cycle inserted
(Initial value)
Bit 1—RAS-CAS Wait (RCW): Controls wait state (Trw) insertion between T_r and T_c1 in DRAM
read/write cycles. The setting of this bit does not affect refresh cycles.
Bit 1
RCW
0
1
Description
Wait state (Trw) insertion disabled
One wait state (Trw) inserted
(Initial value)
Bit 0—Refresh Cycle Wait Control (RLW): Controls wait state (T_RW) insertion for CAS-before-
RAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles.
Bit 0
RLW
0
1
Description
Wait state (T_RW) insertion disabled
One wait state (T ) inserted
RW
(Initial value)
6.2.9 Refresh Timer Control/Status Register (RTMCSR)
Bit
7
6
5
4
3
2
1
0
CMF CMIE CKS2 CKS1 CKS0
—
—
—
Initial value
0
0
0
0
0
1
1
1
Read/Write R(W)* R/W
R/W
R/W R/W
—
—
—
RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When
the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests.
Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes. Bits 5 to 3 are
initialized to 0 by a reset and in hardware standby mode; they are not initialized in software
standby mode.
Rev. 5.0, 09/04, page 131 of 978