3069RF-ZTAT Datasheet, PDF (627/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

(b) Flash pass/fail parameter (FPFR: general register R0L of CPU)
An explanation of FPFR as the return value indicating the erase result is provided here.
Bit :
7
6
5
4
3
2
1
0
0
MD
EE
FK
EB
0
0
SF
Bit 7—Unused: Returns 0.
Bit 6—Erasure Mode Related Setting Error Detect (MD): Returns the check result of whether
the signal input to the FWE pin is high and whether the error protection state is entered.
When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is
written to this bit. The input level to the FWE pin and the error protection state can be confirmed
with the FWE bit (bit 7) and the FLER bit (bit 4) in FCCS, respectively. For conditions to enter
the error protection state, see section 18.6.3, Error Protection.
Bit 6
MD
0
1
Description
FWE and FLER settings are normal (FWE = 1, FLER = 0)
FWE = 0 or FLER = 1, and erasure cannot be performed
Bit 5—Erasure Execution Error Detect (EE): 1 is returned to this bit when the user MAT could
not be erased or when flash-memory related register settings are partially changed on returning
from the user branch processing.
If this bit is set to 1, there is a high possibility that the user MAT is partially erased. In this case,
after removing the error factor, erase the user MAT.
If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is
performed. In this case, both the user MAT and user boot MAT are not erased.
Erasing of the user boot MAT should be performed in the boot mode or PROM mode.
Bit 5
EE
0
1
Description
Erasure has ended normally
Erasure has ended abnormally (erasure result is not guaranteed)
Bit 4—Flash Key Register Error Detect (FK): Returns the check result of FKEY value before
start of the erasing processing.
Rev. 5.0, 09/04, page 605 of 978