3069RF-ZTAT Datasheet, PDF (780/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

21.4.3 Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 21.13 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 21.14 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 21.15 shows the timing of the external three-state access cycle with one wait state
inserted.
Burst ROM access timing/burst cycle: two-state access
Figure 21.16 shows the timing of the two-state burst cycle.
Burst ROM access timing/burst cycle: three-state access
Figure 21.17 shows the timing of the three-state burst cycle.
Burst release mode timing
Figure 21.18 shows the timing in bus release mode.
Rev. 5.0, 09/04, page 758 of 978