3069RF-ZTAT Datasheet, PDF (986/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Modes 3 and 4: Figure D.2 is a timing diagram for the case in which RES goes low during an
external memory access in mode 3 or 4. As soon as RES goes low, all ports are initialized to the
input state. AS, RD, HWR, LWR, and CS₀ go high, and D₁₅ to D₀ go to the high-impedance state.
The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of RES
is sampled. However, when PA₄ to PA₆ are used as address bus pins, or when P8₃ to P8₁ and PB₀ to
PB₃ are used as CS output pins, they go to the high-impedance state at the same time as RES goes
low. Clock pin P6₇/φ goes to the output state at the next rise of φ after RES goes low.
P6₇/φ
Access to external
memory
T1
T2
T3
RES
Internal reset
signal
A₂₀ to A₀
H'000000
CS₀
AS, RD
(read)
HWR, LWR
(write)
D₁₅ to D₀
(write)
High impedance
I/O port,
PA₄/A₂₃ to PA₆/A₂₁,
CS₇ to CS₁
High impedance
Figure D.2 Reset during Memory Access (Modes 3 and 4)
Mode 5: Figure D.3 is a timing diagram for the case in which RES goes low during an external
memory access in mode 5. As soon as RES goes low, all ports are initialized to the input state. AS,
RD, HWR, and LWR go high, and the address bus and D₁₅ to D₀ go to the high-impedance state.
Clock pin P6₇/φ goes to the output state at the next rise of φ after RES goes low.
Rev. 5.0, 09/04, page 964 of 978