3069RF-ZTAT Datasheet, PDF (237/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

7.4 Operation
7.4.1 Overview
Table 7.5 summarizes the DMAC modes.
Table 7.5 DMAC Modes
Transfer Mode
Activation
Notes
Short address
mode
I/O mode
Idle mode
Repeat mode
Compare match/input
•
capture A interrupt from
16-bit timer channels 0 to 2
Up to four channels
can operate
independently
Transmit-data-empty
and receive-data-full
interrupts from SCI
channel 0
• Only the B channels
support external requests
Conversion-end interrupt
from A/D converter
External request
Full address
mode
Normal mode
Auto-request
• A and B channels are
paired; up to two
channels are available
External request
Block transfer mode
Compare match/input
•
capture A interrupt from
16-bit timer channels 0 to 2
Burst mode transfer or
cycle-steal mode transfer
can be selected for auto-
requests
Conversion-end interrupt
from A/D converter
External request
A summary of operations in these modes follows.
I/O Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. A CPU interrupt can be requested at completion of the designated number of
transfers. One 24-bit address and one 8-bit address are specified. The transfer direction is
determined automatically from the activation source.
Idle Mode: One byte or word is transferred per request. A designated number of these transfers
are executed. A CPU interrupt can be requested at completion of the designated number of
transfers. One 24-bit address and one 8-bit address are specified. The addresses are held fixed.
The transfer direction is determined automatically from the activation source.
Rev. 5.0, 09/04, page 215 of 978