3069RF-ZTAT Datasheet, PDF (431/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)
If an increment pulse occurs in the T₃ state of an 8TCNT byte write cycle in 16-bit count mode,
the counter write takes priority and the byte data for which the write was performed is not
incremented. The byte data for which a write was not performed is incremented. Figure 10.24
shows the timing when an increment pulse occurs in the T₂ state of a byte write to 8TCNT (upper
byte). If an increment pulse occurs in the T₂ state, on the other hand, the increment takes priority.
8TCNT (upper byte) byte write cycle
T1
T2
T3
φ
Address bus
8TCNTH address
Internal write signal
8TCNT input clock
8TCNT (upper byte)
N
N+1
8TCNT write data
8TCNT (lower byte)
X
X+1
Figure 10.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
Rev. 5.0, 09/04, page 409 of 978