3069RF-ZTAT Datasheet, PDF (262/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Figure 7.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block
transfer mode.
φ
DREQ
End of 1 block transfer
DMAC cycle
CPU cycle
DMAC cycle
T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T₁ T₂ T_d T₁ T₂
Address
bus
RD
HWR , LWR
TEND
Next sampling
Minimum 4 states
Figure 7.18 Timing of DMAC Activation by Falling Edge of DREQ in Block Transfer Mode
Rev. 5.0, 09/04, page 240 of 978