3069RF-ZTAT Datasheet, PDF (216/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

BRCR Write Timing: Data written to BRCR to switch between A₂₃, A₂₂, A₂₁, or A₂₀ output and
generic input or output takes effect starting from the T₃ state of the BRCR write cycle. Figure
6.51 shows the timing when a pin is changed from generic input to A₂₃, A₂₂, A₂₁, or A₂₀ output.
T1
T2
T3
φ
Address bus
PA7 to PA4
(A23 to A20)
BRCR address
High-impedance
Figure 6.51 BRCR Write Timing
6.11.2 BREQ Pin Input Timing
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes lows, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If
BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
Rev. 5.0, 09/04, page 194 of 978