3069RF-ZTAT Datasheet, PDF (178/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Table 6.5 Settings of Bits DRAS2 to DRAS0 and Corresponding DRAM Space (RAS
Output Pin)
DRAS2 DRAS1 DRAS0 Area 5
Area 4
Area 3
Area 2
0
0
0
Normal space Normal space Normal space Normal space
1
Note:
1
Normal space Normal space Normal space DRAM space
(CS )
2
1
0
Normal space Normal space DRAM space DRAM space
(CS₃)
(CS₂)
1
Normal space Normal space DRAM space DRAM space
(CS₂)*
(CS₂)*
0
0
Normal space DRAM space DRAM space DRAM space
(CS₄)
(CS₃)
(CS₂)
1
DRAM space DRAM space DRAM space DRAM space
(CS )
5
(CS )
4
(CS )
3
(CS )
2
1
0
DRAM space DRAM space DRAM space DRAM space
(CS₄)*
(CS₄)*
(CS₂)*
(CS₂)*
1
DRAM space DRAM space DRAM space DRAM space
(CS₂)*
(CS₂)*
(CS₂)*
(CS₂)*
* A single CS_n pin serves as a common RAS output pin for a number of areas. Unused
CS_n pins can be used as input/output ports.
6.5.3 Address Multiplexing
When DRAM space is accessed, the row address and column address are multiplexed. The
address multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the
number of bits in the DRAM column address. Table 6.6 shows the correspondence between the
settings of MXC1 and MXC0 and the address multiplexing method.
Rev. 5.0, 09/04, page 156 of 978