3069RF-ZTAT Datasheet, PDF (191/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

φ
RTCNT
N
H'00
RTCOR
N
Refresh request signal
and CMF bit setting signal
Figure 6.27 Compare Match Timing
TRp
TR1
TR2
φ
Address bus*
CSn(RAS)
PB₄/PB₅
(UCAS/LCAS)
RD(WE)
RFSH
Area 2 start address
High
AS
High level
Note: * In address update mode 1, the area 2 start address is output.
In address update mode 2, the address in the preceding bus cycle is retained.
Figure 6.28 CBR Refresh Timing (CSEL = 0, TPC = 0, RLW = 0)
The basic CBS refresh cycle timing comprises three states: one RAS precharge cycle (T_RP) state,
and two RAS output cycle (T_R1, T_R2) states. Either one or two states can be selected for the RAS
precharge cycle. When the TPC bit is set to 1 in DRCRB, RAS signal output is delayed by one
cycle. This does not affect the timing of UCAS and LCAS output.
Rev. 5.0, 09/04, page 169 of 978