3069RF-ZTAT Datasheet, PDF (181/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

φ
A23 to A0
AS
CSn (RAS)
Read access
PB₄ /PB₅
(UCAS / LCAS)
RD(WE)
D15 to D0
Write access
PB₄ /PB₅
(UCAS / LCAS)
RD(WE)
D15 to D0
Tp
Tr
Tc1
Tc2
Row
Column
High level
High level
Note: n = 2 to 5
Figure 6.18 Basic Access Timing (CSEL = 0 in DRCRB)
6.5.7 Precharge State Control
In the H8/3069R, provision is made for the DRAM RAS precharge time by always inserting one
RAS precharge state (T_p) when DRAM space is accessed. This can be changed to two T_p states by
setting the TPC bit to 1 in DRCRB. The optimum number of T_p cycles should be set according to
the DRAM connected and the operating frequency of the H8/3069R chip. Figure 6.19 shows the
timing when two T_p states are inserted.
When the TCP bit is set to 1, two T_p states are also used for CAS-before-RAS refresh cycles.
Rev. 5.0, 09/04, page 159 of 978