3069RF-ZTAT Datasheet, PDF (430/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

10.7.6 Contention between TCOR Write and Input Capture
If an input capture signal occurs in the T₃ state of a TCOR write cycle, input capture takes priority
and the write to TCOR is not performed. Figure 10.23 shows the timing in this case.
TCOR write cycle
T1
T2
T3
φ
Address bus
TCOR address
Internal write signal
Input capture signal
8TCNT
M
TCOR
X
M
Figure 10.23 Contention between TCOR Write and Input Capture
Rev. 5.0, 09/04, page 408 of 978