3069RF-ZTAT Datasheet, PDF (208/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

6.9 Idle Cycle
6.9.1 Operation
When the H8/3069R chip accesses external space, it can insert a 1-state idle cycle (T_I) between
bus cycles in the following cases: (1) when read accesses between different areas occur
consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) immediately
after a DRAM space access. By inserting an idle cycle it is possible, for example, to avoid data
collisions between ROM, which has a long output floating time, and high-speed memory, I/O
interfaces, and so on.
The ICIS1 and ICIS0 bits in BCR both have an initial value of 1, so that an idle cycle is inserted in
the initial state. If there are no data collisions, the ICIS bits can be cleared.
Consecutive Reads between Different Areas: If consecutive reads between different areas occur
while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.43 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
φ
Address bus
4,
Data bus
Bus cycle A Bus cycle B
T1 T2 T3 T1 T2
φ
Address bus
Bus cycle A Bus cycle B
T1 T2 T3 Ti T1 T2
4,
Data bus
Long buffer-off ^Data
time
collision
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.43 Example of Idle Cycle Operation (1) (ICIS1 = 1)
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Rev. 5.0, 09/04, page 186 of 978