3069RF-ZTAT Datasheet, PDF (698/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

tosc1
Memory read mode
tbmv ^{Command wait state}
Auto-program mode
Auto-erase mode
Command wait state
Normal/abnormal
end identification _tdwn
V_CC
4-5
FWE
Note: Set the FWE input pin low level, except in the auto-program and auto-erase modes.
Figure 18.36 Oscillation Stabilization Time, PROM Mode Setup Time, and
Power-Down Sequence
18.10.3 Procedure Program and Storable Area for Programming Data
In the descriptions in the previous section, the programming/erasing procedure programs and
storable areas for program data are assumed to be in the on-chip RAM. However, the program
and the data can be stored in and executed from other areas, such as part of flash memory which is
not to be programmed or erased, or somewhere in the external address space.
• Conditions that Apply to Programming/Erasing
(1) The on-chip programming/erasing program is downloaded from the address set by FTDAR in
on-chip RAM, therefore, this area is not available for use.
(2) The on-chip programming/erasing program will use the 128 bytes as a stack. So, make sure
that this area is secured.
(3) Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be
executed in on-chip RAM.
(4) The flash memory is accessible until the start of programming or erasing, that is, until the
result of downloading has been judged. When in a mode in which the external address space
is not accessible, such as single-chip mode, the required procedure programs, NMI handling
vector, NMI handler and user branch program should be transferred to the on-chip RAM
before programming/erasing of the flash memory starts.
(5) The flash memory is not accessible during programming/erasing operations, therefore, the
operation program is downloaded to the on-chip RAM to be executed. The NMI-handling
vector and programs such as that which activate the operation program, user program at the
user-branch destination during programming/erasing operation, and NMI handler should thus
be stored in on-chip memory other than flash memory or the external address space.
(6) After programming/erasing, the flash memory should be inhibited until FKEY is cleared.
The reset state (RES = 0) must be in place for more than 100 µs when the LSI mode is
changed to reset on completion of a programming/erasing operation.
Rev. 5.0, 09/04, page 676 of 978