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3069RF-ZTAT Datasheet, PDF (786/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
21.4.4 DRAM Interface Bus Timing
DRAM interface bus timing is shown as follows:
• DRAM bus timing: read and write access
Figure 21.19 shows the timing of the read and write access.
• DRAM bus timing: CAS before RAS refresh
Figure 21.20 shows the timing of the CAS before RAS refresh.
• DRAM bus timing: self-refresh
Figure 21.21 shows the timing of the self-refresh.
Rev. 5.0, 09/04, page 764 of 978