3069RF-ZTAT Datasheet, PDF (192/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Use the RLW bit in DRCRB to adjust the RAS signal width. A single refresh wait state (T_RW) can
be inserted between the T_R1 state and T_R2 state by setting the RLW bit to 1.
The RLW bit setting is valid only for CBR refresh cycles, and does not affect DRAM read/write
cycles. The number of states in the CBR refresh cycle is not affected by the settings in ASTCR,
WCRH, or WCRL, or by the state of the WAIT pin.
Figure 6.29 shows the timing when the TPC bit and RLW bit are both set to 1.
TRp1
TRP2
TR1
TRW
TR2
φ
Address bus*
CSn(RAS)
PB₄/PB₅
(UCAS/LCAS)
RD(WE)
RFSH
Area 2 start address
High
AS
High level
Note: * In address update mode 1, the area 2 start address is output.
In address update mode 2, the address in the preceding bus cycle is retained.
Figure 6.29 CBR Refresh Timing (CSEL = 0, TPC = 1, RLW = 1)
DRAM must be refreshed immediately after powering on in order to stabilize its internal state.
When using the H8/3069R CAS-before-RAS refresh function, therefore, a DRAM stabilization
period should be provided by means of interrupts by another timer module, or by counting the
number of times bit 7 (CMF) of RTMCSR is set, for instance, immediately after bits DRAS2 to
DRAS0 have been set in DRCRA.
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the
DRAM. The H8/3069R has a function that places the DRAM in self-refresh mode when the chip
enters software standby mode.
Rev. 5.0, 09/04, page 170 of 978