3069RF-ZTAT Datasheet, PDF (611/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Table 18.5 Register/Parameter and Target Mode
Initiali- Program-
RAM
Download zation ming
Erasure Read Emulation
Programming/ FCCS
—
—
—
—
—
erasing
FPCS
—
—
—
—
—
interface
PECS
—
—
—
—
—
registers
FKEY
—
—
—
FMATS —
—
*¹
*¹
*² —
FTDAR
—
—
—
—
—
Programming/ DPFR
—
—
—
—
—
erasing
FPFR —
—
—
interface
FPEFEQ —
—
—
—
—
parameter
FUBRA —
—
—
—
—
FMPAR —
—
—
—
—
FMPDR —
—
—
—
—
FEBS —
—
—
—
—
RAM emulation RAMCR —
—
—
—
—
Notes: 1. The setting is required when programming or erasing user MAT in user boot mode.
2. The setting may be required according to the combination of initiation mode and read
target MAT.
18.4.2 Programming/Erasing Interface Register
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in byte. Except for the FLER bit in FCCS, these registers are initialized at a
power-on reset, in hardware standby mode, or in software standby mode. The FLER bit is not
initialized in software standby mode.
(1) Flash Code Control and Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence
during programming or erasing flash memory and the download of on-chip program.
Bit :
7
6
5
4
3
2
1
0
FWE
—
—
FLER
—
—
—
SCO
Initial value : 1/0
0
0
0
0
0
0
0
R/W :
R
R
R
R
R
R
R
(R)W
Rev. 5.0, 09/04, page 589 of 978