3069RF-ZTAT Datasheet, PDF (250/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

7.4.6 Block Transfer Mode
In block transfer mode the A and B channels are combined. One block of a specified size is
transferred per request. A designated number of block transfers are executed. Addresses are
specified in MARA and MARB. The block area address can be either held fixed or cycled.
Table 7.10 indicates the register functions in block transfer mode.
Table 7.10 Register Functions in Block Transfer Mode
Register
23
MARA
Function
0 Source address
register
Initial Setting
Source start
address
23
MARB
0 Destination
address register
Destination start
address
7
0 _{Block size counter Block size}
ETCRAH
7
0 Initial block size
ETCRAL
15
ETCRB
0 ^{Block transfer}
counter
Block size
Number of block
transfers
[Legend]
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
ETCRB: Execute transfer count register B
Operation
Incremented or
decremented once per
transfer, or held fixed
Incremented or
decremented once per
transfer, or held fixed
Decremented once per
transfer until H'00 is
reached, then reloaded
from ETCRL
Held fixed
Decremented once per
block transfer until H'0000
is reached and the
transfer ends
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred. One of these registers operates as a
block area register: even if it is incremented or decremented, it is restored to its initial value at the
end of each block transfer. The TMS bit in DTCRB selects whether the block area is the source or
destination.
Rev. 5.0, 09/04, page 228 of 978