3069RF-ZTAT Datasheet, PDF (983/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

Hardware
Pin
Standby Software Standby
Name Mode Reset Mode
Mode
Bus-Released
Mode
Program Execution
Mode
PB₃ 1 to 5 T
T
RAS₄ output*¹²
(SSOE=0)
T
(SSOE=1)
H
CS output*¹³
(SSOE=0)
T
(SSOE=1)
H
Otherwise*¹⁴
Keep
RAS₄ output*¹²
T
CS output*¹³
T
Otherwise*¹⁴
Keep
RAS₄ output
RAS₄
CS output
CS₄
Otherwise
I/O port
7
T
T
Keep
—
I/O port
PB₅, 1 to 5 T
T
PB₄
CAS output*¹⁵
(SSOE=0)
T
(SSOE=1)
H
Otherwise*¹⁶
Keep
CAS output*¹⁵
T
Otherwise*¹⁶
Keep
CAS output
UCAS, LCAS
Otherwise
I/O port
7
T
T
Keep
—
I/O port
PB₇, 1 to T
T
PB₆ 5, 7
Keep
Keep
I/O port
[Legend]
H: High
L:
Low
T:
High-impedance state
Keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register
Notes: 1. When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all
cleared to 0.
2. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
set to 1.
3. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is 010, 100, or 101.
4. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 010, 100, 101, or 000.
5. When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
cleared to 0.
6. When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
set to 1.
7. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to 1.
8. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is cleared
to 0.
Rev. 5.0, 09/04, page 961 of 978