3069RF-ZTAT Datasheet, PDF (779/1003 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

21.4.2 Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 21.11 shows the reset input timing.
• Interrupt input timing
Figure 21.12 shows the interrupt input timing for NMI and IRQ₅ to IRQ₀.
φ
RES
FWE
MD₂ to MD₀
t_RESS
t_MDS
t_RESS
t_RESW
Figure 21.11 Reset Input Timing
φ
NMI
IRQ _E
IRQ _L
t_NMIS t_NMIH
t_NMIS t_NMIH
t_NMIS
IRQ _E: Edge-sensitive IRQ _i
IRQ _L : Level-sensitive IRQ _i (i = 0 to 5)
NMI
t_NMIW
IRQ _j
(j = 0 to 5)
Figure 21.12 Interrupt Input Timing
Rev. 5.0, 09/04, page 757 of 978